Recent University of Illinois computer science alumnus Smruti Sarangi and his advisor, professor Josep Torrellas, have published a new text based on Sarangi's doctoral thesis work. Techniques to Mitigate the Effects of Congenital Faults in Processors presents an architecture to patch design defects in processors in the field, and a model of how parameter variation affects timing errors in processors.
As processor architectures become increasingly complex with each subsequent generation, it becomes increasingly difficult to verify processors and guarantee subsequent reliable operation, say the authors. As a consequence, the market is seeing an increase in the number of design defects like logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults, say Sarangi and Torrellas.
Their new text characterizes and proposes solutions to mitigate the effects of such congenital faults. Through their research, the team characterized RTL defects for 10 state of the art processors, and subsequently discovered common patterns and designed an architecture able to patch design defects in processors in the field, thus preventing faults from manifesting. The architecture is called Phoenix.
Further, the text proposes a model called VARIUS of how parameter variation affects timing errors, and then techniques to redress the problem of process variation using a fuzzy logic based architecture.
The text is available for purchase on Amazon.com.